Non-destructive methods for testing integrated circuits are known in the art of semiconductor fabrication. Integrated circuits are generally grown layer by layer into a plurality of many chips dies grouped on thin planar substrates called wafers. Before the wafer is cut into individual chips, the circuitry must be inspected and checked.
Chip circuit testing is usually performed while the chip circuits still reside together on a single wafer, since testing after the dies are sawed apart and packaged is prohibitively expensive. Hundreds of separate chip devices on every wafer are analyzed by passing input signals into each device and monitoring voltage levels at selected output locations.
Conventional probe devices now used often produce inaccurate results because of faulty electrical connections between a test probe and an input/output pad of a chip device under test (DUT). Previous versions of membrane probe test equipment use electrical contacts that are pressed against contact pads on a chip residing on a silicon wafer; these pads are usually made of aluminum.
Aluminum surfaces are usually coated with layers of electrically non-conductive aluminum oxide; these layers are typically five to ten nanometers in depth. This insulative film impairs the capacity of a test probe to accurately and reliably drive high frequency signals into circuitry residing on a wafer.
Problems exist with current technology. Specifically, difficulty has been encountered in providing reliable test systems capable of testing integrated circuits at high speed with while simultaneously maintaining high test accuracy. A major cause of test inaccuracy is the high degree of electrical resistance presented by an oxide film to the flow of electric current.
Therefore, a need exists for the development of an improved membrane test probe which would function well in the face of this oxide resistance.
The invention disclosed here is a test probe system for providing an oxide-abrading scrubbing motion to scrub the contacts residing on a membrane probe card. This probe card is used for supplying high speed test signals to an integrated circuit chip while bundled with other chips on a wafer. This innovative technique improves performance of existing membrane probe card designs by reducing inaccurate test results caused by failure of probe card contacts to make electrical contact with input/output pads of a device under test.